Multi-Gigahertz Testing of Wafer-Level Packaged Devices

The authors are developing alternative approaches for wafer-level packaging (WLP) of high-performance, high I/O-density chips. The electrical contacts are patterned onto the wafer surface using lithographic processes in order to provide high density I/Os at a very low cost per pin. In order to fully exploit these new packaging technologies, a compatible testing approach is also needed. This paper describes one of the WLP I/O structures, a new bare-die test socket, and a low-cost multi-GHz miniature tester. Our initial objective for this WLP technology is 5 Gbps; and the operation of interconnects, the bare-die test socket, and the miniature tester at this rate and slightly higher (6.4 Gbps), was demonstrated. The miniature tester alone is demonstrated up to 8 Gbps