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Efficient Latch and Clock Structures for System-on-Chip Test Flexibility

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1 Author(s)
Lackey, D.E. ; Microelectron. Div., IBM, Essex Junction, VA

This paper describes a novel implementation of edge-triggered flip-flops that incorporates the most optimum features of the leading design-for-testability (DFT) methods in the industry in a manner that is efficient from the standpoint of performance, power and area. The result is a flip-flop design that provides testability that is free of timing hazards (race-free and LSSD compatible), while operating at product frequency using only a single edge clock

Published in:

Test Conference, 2006. ITC '06. IEEE International

Date of Conference:

Oct. 2006