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Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing

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4 Author(s)
Liau Chee Hong, E. ; Infineon Technol. AG, Neubiberg ; Menke, M. ; Janik, T. ; Schmitt-Landsiedel, D.

This paper describes a novel computational intelligence test method with automatic pattern size reduction algorithm - Pattern Pruner for improving the efficiency of localization for the design weaknesses and/or faults using state-of-art automatic test equipment (ATE). Computational intelligence and Pattern Pruner software implemented on semiconductor automatic test equipment allows finding worst case test pattern and identifying design weaknesses. This is demonstrated by detection of a hang-up in a pseudo-SRAM test chip with asynchronous operation and hidden refresh, package parasitics are found to be the cause of the failure, and debugging is performed by modification of the power network

Published in:

Test Conference, 2006. ITC '06. IEEE International

Date of Conference:

Oct. 2006

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