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Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System

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4 Author(s)
Becker, J.E. ; Inst. for Inf. Process. Technol., Karlsruhe Univ. ; Bieser, C. ; Becker, J. ; Mueller-Glase, K.-D.

Due to the rising complexity of modern chip designs, the connection of the different on-chip IP cores has become an important issue. To establish communication links between computation nodes either wide busses or fast serial data paths - so called networks on chip (NoC) - are necessary, depending on the application and the chip design. In case of the serial links a variety of different algorithms and topologies are cogitable, which have to be evaluated and tested to find the optimal solution for a given problem. To do this, the NoC can be emulated on a hardware platform based on FPGAs to exploit the flexibility for short turn-around-times and achieve nearly real time conditions by accelerating the test process. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient network on chip (NoC) implementation based on Xilinx Virtex-II FPGAs

Published in:

Industrial Electronics, 2006 IEEE International Symposium on  (Volume:4 )

Date of Conference:

9-13 July 2006