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A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers

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2 Author(s)
Ding-Lan Shen ; Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei ; Tai-Cheng Lee

A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm2

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 2 )