By Topic

A Model for Wafer Fabrication Dynamics in Integrated Circuit Manufacturing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Judith E. Dayhoff ; Judith Dayhoff & Associates, Inc., Box 4029, Mountain View, CA 94040, USA ; Robert W. Atherton

Integrated circuit manufacturing has major operations of fabrication, sort, assembly, and test. The dynamic behavior of these operations can be modeled in terms of a highly structured queueing network. A model is presented of the components and interactions of wafer movements, processing equipment, and process steps. The model considers multiple process flows, fab organization and layout, and equipment properties such as batch size, process time, failure, and repair distributions. The model is implemented as a discrete event simulation and has been used in a number of case studies concerning realistic factory situations. This simulation model is general and can be used to study many types of discrete manufacturing.

Published in:

IEEE Transactions on Systems, Man, and Cybernetics  (Volume:17 ,  Issue: 1 )