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Valve Damping Circuit Design for HVDC Systems

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2 Author(s)
Y. Beausejour ; INRS-Energy University of Quebec ; G. Karady

This paper presents a method of calculating the recovery overvoltages in a HVDC circuit and the optimization of the damping circuit by selecting the lowest value of the damping circuit capacitance and the resistance which together satisfactorily limit the recovery voltage. Furthermore, a new method is developed for exact calculation of the losses in the damping circuit using a hybrid computer. The effect of the bridge operation (commutating and delay angles) and damping circuit parameters on the losses are analyzed using numerical examples. Finally, a method for designing the valve damping circuit is presented.

Published in:

IEEE Transactions on Power Apparatus and Systems  (Volume:PAS-92 ,  Issue: 5 )