By Topic

A self-timed approach to VLSI digital filter design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
L. Merani ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; S. -L. Lu

A request-acknowledge protocol is normally used for self-timed digital design. The two major philosophies for such a protocol are two-cycle and four-cycle. Data flow graphs have seven primitives. The design of these primitives for both two-cycle and four-cycle protocols is presented. Results of simulations of a multirate comb filter used as a decimator for both of these schemes are also presented. The authors demonstrate not only the efficacy of the synthesis procedure considered but also the improved efficiency of the two-cycle scheme over the four-cycle scheme

Published in:

Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on  (Volume:2 )

Date of Conference:

19-21 May 1993