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A self-timed approach to VLSI digital filter design

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2 Author(s)
Merani, L. ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Shih-Lien Lu

A request-acknowledge protocol is normally used for self-timed digital design. The two major philosophies for such a protocol are two-cycle and four-cycle. Data flow graphs have seven primitives. The design of these primitives for both two-cycle and four-cycle protocols is presented. Results of simulations of a multirate comb filter used as a decimator for both of these schemes are also presented. The authors demonstrate not only the efficacy of the synthesis procedure considered but also the improved efficiency of the two-cycle scheme over the four-cycle scheme

Published in:

Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on  (Volume:2 )

Date of Conference:

19-21 May 1993