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Efficient functional verification algorithm for Petri-net-based parallel controller designs

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3 Author(s)
K. Bilinski ; Dept. of Electr. & Electron. Eng., Bristol Univ., UK ; J. M. Saul ; E. L. Dagless

A new algorithm for verifying the equivalence of parallel controller designs is presented along with its implementation. The controller is specified using a Petri net and its implementation is given as a netlist. The reachability graph of the Petri net is generated and simultaneously the network is implicitly simulated. By exploiting information from the reachability graph a reduction of the time and memory needed for verification has been achieved. Experimental results show that this approach is especially appropriate for parallel controller verification

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IEE Proceedings - Computers and Digital Techniques  (Volume:142 ,  Issue: 4 )