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Short-circuit power driven gate sizing technique for reducing power dissipation

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2 Author(s)
Uming Ko ; Texas Instrum. Inc., Dallas, TX, USA ; Balsara, P.T.

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:3 ,  Issue: 3 )