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Realizing a high measure of confidence for defect level analysis of random testing [VLSI]

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3 Author(s)
Wen-Ben Jone ; Dept. of Comput. Sci. & Inf. Eng., Nat. Chung-Cheng Univ., Chiayi, Taiwan ; Paresh Gondalia ; A. Gutjahr

The defect level in circuit testing is the percentage of circuits, such as chips, which are defective and shipped for use after testing. In this work, it is demonstrated that the defect level of testing a circuit using random patterns should have a probability distribution rather than just a single value. Based on this concept, the confidence degree of a specified defect level for random testing can be derived, and the quality of circuit random testing is thus guaranteed. Results obtained based on random testing can be extended to other test methods, e.g., deterministic testing, pseudo-random testing, or functional testing. Experiments using computer simulation have been conducted for this work, and the results are very encouraging.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:3 ,  Issue: 3 )