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The switch-level model provides a logical abstraction from the physical structure of a metal-oxide semiconductor(MOS) circuit to its digital behavior. At the switch level, a circuit is modeled as a network of transistor switches connecting a set of charge storage nodes. Node voltages are represented by discrete logic levels, and electrical behavior is modeled in a highly simplified way. Switch-level algorithms have been applied to such tasks as logic and fault simulation, formal hardware verification, timing analysis, and automatic test program generation. They have been implemented on sequential and parallel computers as well as by hardware simulation accelerators.