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Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term Â¿macro testing.Â¿ The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.