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SMART And FAST: Test Generation for VLSI Scan-Design Circuits

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4 Author(s)

This article describes new concepts and algorithms used to generate tests for VLSI scan-design circuits. The new algorithms include: 1. a low-cost fault-independent algorithm (SMART), 2. a fault-oriented algorithm (FAST), and 3. an algorithm for dynamic test set compaction. The fault-oriented algorithm is guided by new controllability/observability cost functions whose objective is to minimize the amount of search done in test generation.

Published in:

Design & Test of Computers, IEEE  (Volume:3 ,  Issue: 4 )