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Memory test timesÂ¿and thus test costsÂ¿are increasing rapidly as the size of the memories grows each year. Testability techniques therefore must be developed to reduce the test time without compromising the test quality. This article presents an approach that meets this goal using parallel signature analyzers (PSAs). PSAs can access more data cells in parallel than I/O pins can, and the approach's parallelism reduces the test time. The proposed method is analyzed with respect to test time, test quality, and silicon area penalty.