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A New Economical Implementation for Scannable Flip-Flops in MOS

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1 Author(s)
Bhavsar, D.K. ; Digital Equipment Corporation

A New implementation for scannable flip-flops in MOS is economical for use in systems that use single latch design. The ¿System Latch-Scannable Flop¿ (SL-SF) requires two additional transfer gates, two test clocks, and possibly a test mode signal. Hardware pernalties paid in SL-SF can be the least among other implementations with equivalent test functionality. This article discusses SL-SF only in the context of its scan-path implementation; its applicability to linear feedback shift-register-based self-test should be obvious.

Published in:

Design & Test of Computers, IEEE  (Volume:3 ,  Issue: 3 )