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We will describe a wirelist compare program that, together with a VLSI node extractor, is used to verify VLSI IC layout connectivity. Engineers at Digital Equipment Corporation have successfully used this tool in a production environment to debug layout errors. The program is based on a graph isomorphism algorithm and provides graphical and textual guides to pinpoint errors. We will examine this algorithm, its error outputs, and provide run-time statistics.
Date of Publication: June 1986