Referenced Items are not available for this document.
We will describe a wirelist compare program that, together with a VLSI node extractor, is used to verify VLSI IC layout connectivity. Engineers at Digital Equipment Corporation have successfully used this tool in a production environment to debug layout errors. The program is based on a graph isomorphism algorithm and provides graphical and textual guides to pinpoint errors. We will examine this algorithm, its error outputs, and provide run-time statistics.
Published in:
Design & Test of Computers, IEEE
(Volume:3
,
Issue:
3
)
Date of Publication: June 1986
- Page(s):
- 46 - 51
- ISSN :
- 0740-7475
- Digital Object Identifier :
- 10.1109/MDT.1986.294992
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 23 July 2007
- Issue Date :
- June 1986
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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