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An Automatic DFT System for the Silc Silicon Compiler

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2 Author(s)
Fung, H.S. ; GTE Laboratories, Inc. ; Hirschhorn, S.

This article discusses design for testability automation for the Silc silicon compiler under development at GTE Laboratories, Inc. Our modular design for testability uses both built-in self-test and scan-path techniques for Slic's full custom VLSI designs. A test controller coordinates the testing of the chip's modules. Testability evaluation is performed using controllability/observability methods, and using a method based on information theory. A testable-by-construction approach is followed in order to synthesize blocks of testable logic. A testability ¿expert¿ manages testability knowledge during the synthesis process and makes the ultimate testability decisions.

Published in:

Design & Test of Computers, IEEE  (Volume:3 ,  Issue: 1 )

Date of Publication:

Feb. 1986

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