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An Automatic Test-Generation System for Large Digital Circuits

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2 Author(s)
Funatsu, S. ; NEC Corporation ; Kawai, M.

A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.

Published in:

Design & Test of Computers, IEEE  (Volume:2 ,  Issue: 5 )

Date of Publication:

Oct. 1985

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