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The article describes a new approach to the self-testing and testability analysis of the types of logic structure encountered in the data flow paths of computers. The main purpose of the new methodology is to avoid the costs associated with manual or automatic test pattern generation. Instead of relying upon an automated process of scanning through a gatelevel description of the logic, this is an analytical approach applied to a block-level functional description of the logic structure. This approach allows a hybrid test technique to be adopted, based on both random and pseudoexhaustive test styles, and gives fault coverage figures in excess of 99.5 percent. The methodology is suitable only for highly structured and well-partitioned logic designs.