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Hierarchical Layout Verification

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1 Author(s)
Wagner, T.J. ; Intel

This article presents a hierarchical cell structure that has been Used successfully to improve the performance of Intel's connectivity verifier and design rule checker. A unique algorithm for performing design rule checks efficiently in a hierarchical environment is discussed in detail. To undersize and oversize in a hierarchical environment without disrupting the cell structure, the definition of sizing must be changed so that geometries inside a cell and touching the cell boundaries do not pull away and geometries outside the cell do not extend inside. There are also a few Pathologies¿caused mostly by looking at only a small portion of the layout, outside of the context where it is used. Nevertheless, careful use of hierarchical design can deliver order-of-magnitude improvements in layout checking runtime.

Published in:

Design & Test of Computers, IEEE  (Volume:2 ,  Issue: 1 )