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Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design

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5 Author(s)
Toshiki Kanamoto ; RENESAS technology; Osaka University, E-mail: kanamoto.toshiki@renesas.com ; Tatsuhiko Ikeda ; Akira Tsuchiya ; Hidetoshi Onodera
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This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (finite element method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow

Published in:

2006 IEEE Workship on Signal Propagation on Interconnects

Date of Conference:

9-12 May 2006