By Topic

A Loss Optimization Method Using WD Product for On-Chip Differential Transmission Line Design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hiroyuki Ito ; Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503 Japan, Tel. & Fax.: +81-45-924-5031, E-mail: ; Kenichi Okada ; Kazuya Masu

This paper proposes a loss optimization method for a high-speed transmission line on Si LSI. One of the most important issues for a transmission line interconnection is loss reduction of signal lines. Characteristics of differential transmission lines are evaluated by on-wafer measurement. It is shown that attenuation characteristics depend on the product of a line width and a line-to-line distance. The simple attenuation model is proposed

Published in:

2006 IEEE Workship on Signal Propagation on Interconnects

Date of Conference:

9-12 May 2006