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A Loss Optimization Method Using WD Product for On-Chip Differential Transmission Line Design

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3 Author(s)
Ito, H. ; Inst. of Integrated Res., Tokyo Inst. of Technol., Yokohama ; Okada, K. ; Masu, K.

This paper proposes a loss optimization method for a high-speed transmission line on Si LSI. One of the most important issues for a transmission line interconnection is loss reduction of signal lines. Characteristics of differential transmission lines are evaluated by on-wafer measurement. It is shown that attenuation characteristics depend on the product of a line width and a line-to-line distance. The simple attenuation model is proposed

Published in:

Signal Propagation on Interconnects, 2006. IEEE Workshop on

Date of Conference:

9-12 May 2006