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A Loss Optimization Method Using WD Product for On-Chip Differential Transmission Line Design

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3 Author(s)
Hiroyuki Ito ; Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503 Japan, Tel. & Fax.: +81-45-924-5031, E-mail: itohiro@lsi.pi.titech.ac.jp ; Kenichi Okada ; Kazuya Masu

This paper proposes a loss optimization method for a high-speed transmission line on Si LSI. One of the most important issues for a transmission line interconnection is loss reduction of signal lines. Characteristics of differential transmission lines are evaluated by on-wafer measurement. It is shown that attenuation characteristics depend on the product of a line width and a line-to-line distance. The simple attenuation model is proposed

Published in:

2006 IEEE Workship on Signal Propagation on Interconnects

Date of Conference:

9-12 May 2006