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Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

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2 Author(s)
Ki-Heung Park ; Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Daegu ; Jong-Ho Lee

We proposed a new bulk FinFET that has a p+/n+ poly-Si gate consists of p+ region near the source and n+ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n+ poly-Si gate length (Ls). For given gate length (Lgles50 nm) and fin body width (Wfinles30 nm), Ls was designed to satisfy the I off requirement (i.e., 1 fA) of DRAM cell. Optimum Ls /Lg of 30-nm device was ~0.4 at a Wfin of 10 nm and ~0.2 at a Wfin of 15 nm

Published in:

IEEE Electron Device Letters  (Volume:28 ,  Issue: 2 )