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Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

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2 Author(s)
Kranti, Abhinav ; Sch. of Electr. & Electron. Eng., Queen''s Univ., Belfast ; Armstrong, G.A.

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (AVO) and cutoff frequency (fT ) of 25-nm gate-length FinFETs operated at low drain-current (I ds=10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of AVO (~45 dB) and f T (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 2 )

Date of Publication:

Feb. 2007

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