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A Wiring-Efficient, High-Throughput Low Density Parity Check Decoder Design

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2 Author(s)
Zarubica, R. ; Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA ; Wilson, S.G.

A high-throughput 1020-bit rate-1/2 low density parity check (LDPC) decoder design is proposed that matches the coding gain of current LDPC decoders. The decoder features wiring-efficient code design and an unwrapping technique that allows us to trade between size and the throughput of a decoder.

Published in:
Information Sciences and Systems, 2006 40th Annual Conference on

Date of Conference: 22-24 March 2006

Page(s):
818 - 822
E-ISBN :
1-4244-0350-2
Print ISBN:
1-4244-0349-9
INSPEC Accession Number:
9528351
Conference Location :
Princeton, NJ
Digital Object Identifier :
10.1109/CISS.2006.286580
Product Type:
Conference Publications

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