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Enhancement of Memory Performance Using Doubly Stacked Si-Nanocrystal Floating Gates Prepared by Ion Beam Sputtering in UHV

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7 Author(s)
Kyu Il Han ; Dept. of Phys. & Appl. Phys., Kyung Hee Univ., Yongin ; Yong Min Park ; Sung Kim ; Suk-Ho Choi
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Structures of SiO2/SiOx/SiO2 and SiO2/SiOx/SiO2/SiOx/SiO 2 have been prepared on Si wafers by ion beam sputtering deposition in ultrahigh vacuum (UHV) and subsequently annealed to form single-layer and doubly stacked Si nanocrystals (NCs). Using these two structures, nonvolatile Si-NC floating-gate nMOSFETs were fabricated at x=1.6 following 1.5-mum CMOS standard procedures. The Fowler-Nordheim tunneling of the electrons through the tunnel oxide, their storage into NCs, retention, and endurance are all investigated by varying the device structure and the thicknesses of the NC and oxide layers. It is shown that charge-retention time is longer, and program/erase (P/E) speeds are faster in doubly stacked devices than in single-layer devices, which seem to result from the optimization of device structure, the exclusion of unwanted defects due to the nature of UHV, and the suppression of charge leakage by the multiple barriers/NC layers in the doubly stacked devices. It is also found that the threshold voltages in the endurance characteristics anomalously increase with the P/E cycles, more strongly in the doubly stacked NC memories

Published in:

Electron Devices, IEEE Transactions on  (Volume:54 ,  Issue: 2 )

Date of Publication:

Feb. 2007

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