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Exploiting multicycle false paths in the performance optimization of sequential logic circuits

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3 Author(s)
Ashar, P. ; C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA ; Dey, S. ; Malik, S.

This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:14 ,  Issue: 9 )

Date of Publication:

Sep 1995

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