By Topic

A CMOS combinational circuit-design method using mixed logic concepts

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hudson, W.B. ; Dept. of Electr. & Comput. Eng., Kansas State Univ., Manhattan, KS, USA ; Beasley, J.S. ; Steelman, J.E.

Presented in this paper is a method which can be used for the implementation of CMOS transistor combinational circuit design using mixed logic digital design techniques. The mixed logic method presented in this paper provides a systematic way of developing minimal transistor count combinational circuits. Additionally, students find the straight forward rules associated with the mixed logic design method allows them to quickly develop CMOS combinational circuit design skills. Examples of the circuit realizations developed using mixed and positive logic design methods as well as a comparison of the design methods are presented in this paper

Published in:

Education, IEEE Transactions on  (Volume:38 ,  Issue: 3 )