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A CMOS combinational circuit-design method using mixed logic concepts

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3 Author(s)
W. B. Hudson ; Dept. of Electr. & Comput. Eng., Kansas State Univ., Manhattan, KS, USA ; J. S. Beasley ; J. E. Steelman

Presented in this paper is a method which can be used for the implementation of CMOS transistor combinational circuit design using mixed logic digital design techniques. The mixed logic method presented in this paper provides a systematic way of developing minimal transistor count combinational circuits. Additionally, students find the straight forward rules associated with the mixed logic design method allows them to quickly develop CMOS combinational circuit design skills. Examples of the circuit realizations developed using mixed and positive logic design methods as well as a comparison of the design methods are presented in this paper

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IEEE Transactions on Education  (Volume:38 ,  Issue: 3 )