A High-Speed Network Interface Design for Packet-Based NoC

In this paper, we propose an interface design which supports serial-link packet-based transmission model for network-on-chip application The interface function consists of packet construction, flow control, error detect, re-transmission mechanism, data scrambler and 8b/10b transformation. The whole function is partitioned into three layers and designed as a peer-to-peer architecture. Every layer can be further divided into a transmitting portion that processes outbound traffic and a receiving portion that processes inbound traffic. We also simulate the buffer requirement with different transmission parameters. Finally, the layout area of network interface is about 0.43 mm² based on 0.13 mum CMOS technology.