Low-Power Content Addressable Memory Using 2N-2N2P Circuits

In this paper, we present a novel low power adiabatic content-addressable memory (CAM). It consists of a CAM-cell array, address decoders, read/write control circuits, sense amplifiers, read/write drivers and compare circuits. An AC power supply is used for driving the match-lines to reduce the energy consumption in adiabatic manner. The rest circuits employ 2N-2N2P circuits to recover the charge of node capacitances on address decoders, bit-lines and word-lines. The power consumption of compare operation is significantly reduced because the energy transferred to the capacitance buses is mostly recovered. The energy and functional simulations of a 16 x 16 CAM are performed. SPICE simulations indicate that the proposed CAM attains energy savings of 60% to 80% as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200 Mhz.