By Topic

Low-Power Content Addressable Memory Using 2N-2N2P Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wu Yangbo ; Faculty of Information Science and Technology, Ningbo University, Ningbo 315211, P.R.China. Email: ; Hu Jianping

In this paper, we present a novel low power adiabatic content-addressable memory (CAM). It consists of a CAM-cell array, address decoders, read/write control circuits, sense amplifiers, read/write drivers and compare circuits. An AC power supply is used for driving the match-lines to reduce the energy consumption in adiabatic manner. The rest circuits employ 2N-2N2P circuits to recover the charge of node capacitances on address decoders, bit-lines and word-lines. The power consumption of compare operation is significantly reduced because the energy transferred to the capacitance buses is mostly recovered. The energy and functional simulations of a 16 x 16 CAM are performed. SPICE simulations indicate that the proposed CAM attains energy savings of 60% to 80% as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200 Mhz.

Published in:

2006 International Conference on Communications, Circuits and Systems  (Volume:4 )

Date of Conference:

25-28 June 2006