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Efficient Decoder Implementation for QC-LDPC Codes

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5 Author(s)
Jin Sha ; Inst. of VLSI design, Nanjing Univ., Nanjing ; Minglun Gao ; Zhongjin Zhang ; Li Li
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Channel coding is an important building block in communication systems. Low-density parity-check codes is one kind of prominent error correcting codes being considered in next generation industry standards. This paper presents a memory efficient, very high speed decoder architecture suited for quasi-cyclic low-density parity-check codes using modified Min-Sum decoding algorithm. In general, about seventy percent of message memory can be saved over conventional decoder architectures, and the decoding speed can be largely accelerated because of the highly efficient VLSI architecture. Consequently, the proposed approach facilitates the applications of LDPC codes in area/latency sensitive communication systems.

Published in:

Communications, Circuits and Systems Proceedings, 2006 International Conference on  (Volume:4 )

Date of Conference:

25-28 June 2006