By Topic

Low-Power and Low-Complextly Full Adder Design for Wireless Base Band Application

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jin-fa lin ; Department of Electronic Engineering, National Yunlin University of Science & Technology, Touliu, Yunlin, Taiwan ; Ming-hwa Sheu ; Yin-tsung Hwang

A novel full adder design with only 10 transistors is presented targeting low power arithmetic operation for wireless base band processing. To alleviate the multi threshold voltage loss and the speed degradation problems common in 10T full adder designs, an inverter is successfully embedded along the carry path at no extra circuit overhead. It helps restore the logic swing and thus the driving capability to enhance the speed of carry propagation. Post layout simulations in TSMC 2P4M 0.35-mum CMOS process model indicate that the proposed design outperforms in both speed and normalized power consumption aspects among peer 10T full adder designs. The performance edge becomes even bigger when the adders are cascaded for n-bit ripple carry addition. We further compare our design with other higher transistor count full adder designs. The simulations reveal that our design performs comparably well in speed and power metrics but enjoys the advantage of much lower circuit complexity

Published in:

2006 International Conference on Communications, Circuits and Systems  (Volume:4 )

Date of Conference:

25-28 June 2006