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1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- \mu\hbox {m} CMOS Technology

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2 Author(s)
Pyung-Su Han ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul ; Woo-Young Choi

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with the 0.18-mum CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 1 )