Cart (Loading....) | Create Account
Close category search window

A 10-Bit, 40 MSamples/s Low Power Pipeline ADC for System-on-a-Chip Digital TV Application

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Francke, J. ; Dept. of Electron. Eng., Tsinghua Univ., Beijing ; Huazhong Yang ; Rong Luo

A 10-bit, 40 Msample/s ADC for a SoC DTV receiver has been designed. Simulations verify that the required dynamic specification of 9.2 effective bits and a spurious free dynamic range (SFDR) higher than 64dB has been reached. Several unconventional techniques have been applied to achieve low power dissipation: Among others, the normally used sample-and-hold stage has been abandoned and the comparators do not exhibit static currents. The ADC core dissipates less than competitive 18mW static power

Published in:

International Semiconductor Conference, 2006  (Volume:2 )

Date of Conference:

27-29 Sept. 2006

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.