Referenced Items are not available for this document.
A 10-bit, 40 Msample/s ADC for a SoC DTV receiver has been designed. Simulations verify that the required dynamic specification of 9.2 effective bits and a spurious free dynamic range (SFDR) higher than 64dB has been reached. Several unconventional techniques have been applied to achieve low power dissipation: Among others, the normally used sample-and-hold stage has been abandoned and the comparators do not exhibit static currents. The ADC core dissipates less than competitive 18mW static power
Published in:
International Semiconductor Conference, 2006
(Volume:2
)
Date of Conference: 27-29 Sept. 2006
- Page(s):
- 421 - 424
- Print ISBN:
- 1-4244-0109-7
- INSPEC Accession Number:
- 9211190
- Conference Location :
- Sinaia
- Digital Object Identifier :
- 10.1109/SMICND.2006.284035
- Product Type:
- Conference Publications
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