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This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.