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Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design

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4 Author(s)
Ming-Ching Lu ; Sci.-Based Ind. Park, SpringSoft, Inc., Hsinchu ; Meng-Chen Wu ; Hung-Ming Chen ; Hui-Ru Jiang

Using voltage island methodology to reduce power consumption for system-on-a-chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in modules.

Published in:

SOC Conference, 2006 IEEE International

Date of Conference:

24-27 Sept. 2006

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