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H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture

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6 Author(s)
Major, A. ; Sch. of Eng. & Electron., Univ. of Edinburgh, Edinburgh ; Ying Yi ; Nousias, I. ; Milward, M.
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This paper presents a new baseline profile compliant H.264 decoder implementation specifically tailored for an ANSI-C programmable, dynamically reconfigurable, instruction cell based architecture which has been developed. We use the ffmpeg libavcodec library as the basis for our decoder and identify the most processor intensive functions. These functions are tailored in a novel framework incorporating established software techniques alongside several architecture specific transforms. Initial results demonstrate that our reconfigurable architecture based decoder provides a significant performance boost with power figures below that of a microcontroller such as ARM.

Published in:

SOC Conference, 2006 IEEE International

Date of Conference:

24-27 Sept. 2006