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Architecture for Low Power Large Vocabulary Speech Recognition

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3 Author(s)
Dhruba Chandra ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC ; Pazhayaveetil, U. ; Franzon, P.D.

This paper proposes an architecture for real-time large vocabulary speech recognition on a mobile embedded device. The speech recognition system is based on Hidden Markov Model (HMM), which involves complex mathematical operations such as probability estimation and Viterbi decoding. This computational nature makes it power hungry and realtime recognition is not achieved by porting software solutions on embedded device. Our system architecture has a low power embedded processor and dedicated ASIC units for complex computations. These units operate at a low frequency of 50 MHz thus consuming low power. The system uses RAM for the intermediate values and flash memory to store acoustic and language models for speech recognition.

Published in:

SOC Conference, 2006 IEEE International

Date of Conference:

24-27 Sept. 2006