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FinFET SRAM with Enhanced Read / Write Margins

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6 Author(s)
Carlson, A. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA ; Guo, Z. ; Balasubramanian, S. ; Pang, L.T.
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In this work, the impact of this pass-gate feedback (PGFB) technique on cell write-ability is examined, and gate workfunction (Phim) tuning for optimization of the trade-off with read margin is discussed. To further improve cell write-ability, the p-channel pull-up devices can also be operated in BG mode, with their back gates driven by a separate write word line. This pull-up write gating (PUWG) technique is effective for maintaining larger than 6 standard deviations yield down to 0.4V VDD without area penalty, making FinFET-based 6-T SRAM compelling for high-density memory applications

Published in:

International SOI Conference, 2006 IEEE

Date of Conference:

2-5 Oct. 2006

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