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Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

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14 Author(s)
Xiang-zheng Bo ; Austin Silicon Technology Solutions (ASTS), Freescale Semiconductor, Inc., 3501 Ed Bluestein Blvd., Austin, TX 78726; Tel: (512) 933-7087; Fax: (512) 933-6962; Email: ; Paul Grudowski ; Vance Adams ; Konstantin Loiko
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We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations

Published in:

2006 IEEE international SOI Conferencee Proceedings

Date of Conference:

2-5 Oct. 2006