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IC's Performance Improvement and 3D Integration by Layer Transfer Technologies

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2 Author(s)
B. Aspar ; TRACIT Technologies ¿ Zone Astec - 15, rue des Martyrs-38054 Grenoble Cedex 9 ¿ France. Email: ; C. Lagahe-Blanchard

In microelectronics and MEMS (micro electro mechanical systems) industries, complex structures are required to improve IC's performance or to achieve high levels of integration. The level of integration is now so important that we are talking more and more about systems. Different approaches have been developed to obtain such a system. "System in package" relies on the association in a same package of several dies built on different technologies. "System on chip" integrated on single chip different functions or components often built on a similar technology. This limits the possibility of integrating circuits which perform with various technologies. Further integration requires reliable and cost effective solutions for 3D structures allowing ultimately stacking of various IC's on a chip. In this context, direct wafer bonding appears as a key generic technology to increase systems integration but also to achieve original structures difficult to obtain by other methods. Transfers of partially or fully processed layers onto different supports offer plenty of solutions for the fabrication of new structures. Recent results obtained by wafer bonding and thinning down techniques are presented in this paper

Published in:

2006 IEEE international SOI Conferencee Proceedings

Date of Conference:

2-5 Oct. 2006