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A fault tolerance model called triple modular redundancy with standby (TMRSB) is developed which combines the two popular fault tolerance techniques of triple modular redundancy (TMR) and standby (SB) fault tolerance. In TMRSB systems, each module of a TMR arrangement has access to several independent standby configurations. When a fault is detected in a module's active configuration, the physical resources within that module are re-mapped to restore the desired fault-free functionality by reconfiguring the resource pool to one of the standby configurations. A mathematic model for TMRSB systems is developed for field programmable gate array (FPGA) logic devices. Simulation of the model was also performed using the BlockSim reliability software tool which takes into account the reconfiguration time overheads and an imperfect switching mechanism. With component time-to-failure following an exponential distribution throughout long mission duration, the range of operation over which TMRSB is superior to a standby system and a TMR system is shown.