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A mixed-signal model of a 10-bit pipeline ADC is developed using the Verilog language. Transient results for individual cells and the overall converter are calculated by solving the characteristic differential equations using an event driven forward Euler numerical solver. The model includes nonlinearities within the amplifier such as capacitor mismatch and slew rate limiting. Post-processing is done in Matlab. The overall goal of this work is to develop a mixed-signal model to verify and identify design flaws based on ADC input/output tests
Published in:
Behavioral Modeling and Simulation Workshop, Proceedings of the 2006 IEEE International
Date of Conference: 14-15 Sept. 2006
- Page(s):
- 115 - 119
- Print ISBN:
- 0-7803-9742-8
- INSPEC Accession Number:
- 9231495
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/BMAS.2006.283480
- Product Type:
- Conference Publications
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