Referenced Items are not available for this document.
In this work, we simulate silicon-on-insulator (SOI) multiple gate FinFET (MuGFET) with the design targeting for the ITRS 2004 specifications for NMOSFET. A detailed fully 3D simulation and analysis of the parasitic capacitances is performed for the first time to study the impact of scaling and pitch spacing. Unlike planar devices, FinFET scaling does not always result in a straightforward performance improvement due to the current crowding effect and series resistance
Published in:
Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Date of Conference: 6-8 Sept. 2006
- Page(s):
- 252 - 255
- Print ISBN:
- 1-4244-0404-5
- INSPEC Accession Number:
- 9431668
- Conference Location :
- Monterey, CA
- Digital Object Identifier :
- 10.1109/SISPAD.2006.282883
- Product Type:
- Conference Publications
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