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VLSI architecture for discrete wavelet transform

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3 Author(s)
Grzeszczak, A. ; Dept. of Electr. Eng., Ottawa Univ., Ont., Canada ; Yeap, T.H. ; Panchanathan, S.

This paper presents a new VLSI architecture for computing the discrete wavelet transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI

Published in:

Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on

Date of Conference:

25-28 Sep 1994