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A High Performance Soft Decision Viterbi Decoder for Wlan and Broadband Applications

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2 Author(s)
Abdul-rafeeq Abdul-Shakoor ; Communications Research Centre Canada, 3701 Carling Avenue, Box 11490, Station H, Ottawa, Ontario, K2H 8S2, Canada. ; Valek Szwarc

This paper presents a configurable 3-bit soft decision Viterbi decoder implementation that meets the requirements for WLAN and broadband applications. The programmable design supports a constraint length K=7 soft decision Viterbi decoder (SDVD) realization with a code rate (R) of 1/2 and traceback lengths (TBL) of 35 and 50 symbols. To assure a throughput of 155 Mbps, an architecture incorporating 32 add compare select (ACS) units operating in parallel has been selected. The design incorporates a built-in self-test for operation at the rated throughput. The VHDL simulation results are verified against a functional model of the Viterbi decoder reflecting the hardware architecture in the Matlab simulation environment. The decoder architecture is defined in VHDL and the circuit is simulated, synthesized, and implemented on a Xilinx XC2VP100-1704ff-5 FPGA device

Published in:

2006 Canadian Conference on Electrical and Computer Engineering

Date of Conference:

May 2006