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From BSP to a virtual von Neumann machine

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3 Author(s)
Kalantery, N. ; Centre for Parallel Comput., Westminster Univ., London, UK ; Winter, S.C. ; Wilson, D.R.

The BSP (bulk synchronous parallel) architecture incorporates a scalable and transparent communication model. The task-level synchronisation mechanism of the machine, however, is not transparent to the user and can be inefficient when applied to the co-ordination of irregular parallelism. This article presents a discussion of an alternative memory-level scheme which offers the prospect of achieving both efficient and transparent synchronisation. The scheme, based on a discrete-event simulation paradigm, supports a sequential style of programming and, coupled with the BSP communication model, leads to the emergence of a virtual von Neumann parallel computer.<>

Published in:

Computing & Control Engineering Journal  (Volume:6 ,  Issue: 3 )