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Threshold voltage sensitivity of 0.1 μm channel length fully-depleted SOI NMOSFET's with back-gate bias

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2 Author(s)
E. Leobandung ; Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA ; S. Y. Chou

We found threshold voltage sensitivity to silicon thickness variation in 0.1 μm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases

Published in:

IEEE Transactions on Electron Devices  (Volume:42 ,  Issue: 9 )