By Topic

Architectures for high performance digital control processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Habib Istepanian, R.S. ; Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK ; Goodall, R.M. ; Jones, S.R.

This paper reports on a research project which is developing algorithms and architectures for a control system processor (CSP). The design considerations given suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used as an example to illustrate some of the issues. The problem of an optimal realization of digital controllers taking into account finite wordlength issues is investigated within the framework of the delta (δ) operator formulation, which provides improved numerical capabilities with high sampling rate, fixed point computations and improved I/O requirements

Published in:

Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures, IEE Colloquium on (Digest No.1995/116)

Date of Conference:

31 May 1995